The present disclosure relates to a semiconductor device, and, in particular, relates to a semiconductor device provided with a test mode.
In order to facilitate a functional test of a RAM mounted in a custom LSI, a BIST (Built-in Self Test) circuit has been attracting attention. In this technique, a test circuit (BIST circuit) is mounted in an LSI, and a RAM test is automatically performed inside the LSI. The BIST circuit has the following advantages.
An expensive tester is not required (it is not necessary to generate a test pattern in the external of the LSI). In the test of a RAM for which a direct test from the external of the LSI is difficult, high quality of the test (a high degree of the failure detection rate) is obtained. Since the BIST circuit is mounted in a chip, it is necessary that the BIST circuit itself can be realized with a small amount of hardware. It is also necessary that the BIST circuit itself can support various kinds of word-bit configurations flexibly, in order to satisfy the specification of a RAM used.
In this respect, a marching test is well know as one of the tests of a RAM (Patent Literatures 1 and 2).
It is said that the marching test is effective in the detection of a cell failure. Specifically, it is possible to detect the inter-cell interference such as interference to other surrounding cells, due to short-circuit with an adjacent cell, sneaking from a sense line, or leak of a defective cell.
In order to execute the marching test, in the general method, a test pattern of read and write of a memory cell is executed in all the addresses one by one, and it is possible to detect whether data of an adjoining un-selected memory cell is not reversed when data write is executed to a memory cell of a certain selected address.
(Patent Literature 1) Japanese Unexamined Patent Application Publication No. Hei 5(1993)-342113
(Patent Literature 2) Japanese Unexamined Patent Application Publication No. Hei 6(1994)-325600